Data converters for converting analog data to digital data utilize an analog-to-digital converter of the successive approximation type and operating with a SAR algorithm. These converters utilize a switched capacitor array that is binary weighted for redistributing charge. The binary weighted capacitor array has a plurality of capacitors, each having a top plate connected to a common node and a bottom plate, each capacitor having the associated bottom plate connected to individual switches. The bottom plates of the capacitors are switched between a reference voltage, an input voltage and ground, depending upon the particular SAR algorithm. This is conventional. Each of the capacitors ranges from a first value of C, a second value of 2C, a third value of 4C, a fourth value of 8C, etc., in a binary weighted manner. In order to ensure that the capacitor ratios are correct, these capacitors are typically configured with the use of a plurality of unit capacitors of value “C.” Thus, the first capacitor will be a single capacitor value “C” utilizing a single unit capacitor. The next capacitor, the 2C capacitor, will require a value of “2C” requiring two unit capacitors of value “C.” The next capacitor in the binary sequence will be four unit capacitors to give a total value of “4C,” the next one being eight unit capacitors for a total of “8C,” and so on. Each of these C, 2C, 4C, 8C, . . . , capacitors is comprised of a sub array of unit capacitors, where “C” ins the unit capacitance value. It is important when manufacturing the unit capacitors and interconnecting them to form the unit capacitor sub arrays that the capacitance values be true, i.e., that the 8C capacitor be exactly eight times the value of the unit capacitor 1C. Since the capacitors are typically configured in some type of bulk array and are disposed typically in association with other capacitors, some in the associated sub array and some associated with other sub arrays, there will be certain characteristics that must be considered. For example, the first capacitor in the array is a single unit capacitor value “C.” The capacitor 4C will have four unit capacitors. If these unit capacitors are disposed in a 2×2 array, this will mean that four of the capacitors will have two exposed sides with the other two sides being associated with adjacent capacitors in other sub arrays. This could result in a different capacitance value in total than the expected 4C value. Thus, the design of the capacitive array must account for various parasitics and the such in the design thereof.